The invention relates to memories made in integrated circuit form and, more particularly, circuits for the activation of redundant columns.
The greater the storage capacity of a memory, and the more precision-oriented its integration technology, the more these memories are subject to manufacturing defects. For it is very difficult to obtain, simultaneously, a very small-sized integrated circuit, a very large storage capacity within this small size and high manufacturing efficiency. Just one defect in a memory with a million cells may mean that the memory has to be discarded.
To increase manufacturing efficiency, it is common to use memories having redundancy systems, namely memories having more memory cells than are needed and connection circuits capable of using the additional cells (redundant cells) and require normal cells which turn out to be defective. When the memory is tested, the defective cells are detected and connection paths are set up to disconnect the defective cells and connect the redundant cells in their place, so that the user sees the memory as being good on the whole despite the presence of defective elements.
In principle, memories are organise in rows and columns of cells. At a column conductor (sometimes called a "bit line"), the user reads the information contained in a cell located at the intersection of this column conductor with a determined row defined by a row address.
The redundancy systems commonly used generally do not merely replaced a defective cell by a redundant cell. More usually, they replace a row or a column having one or more defects by a redundant row or column.
In large-capacity memories designed to give data in the form of z-bit words, the number of columns is typically far greater than z. For example, even if 8-bit, 16-bit or 32-bit words are to be given at the output of the memory, the total number of columns may be 512. In this case, the columns are arranged in z sets of columns, each set corresponding to a data output contact of the memory. At each contact and in each reading operation, there is collected a piece of data coming from a determined column of a set corresponding to this contact and not to another one. There are z contacts and z sets: one contact per set.
It will be noted, in passing, that throughout the rest of this description, we shall consider only the aspect of the reading of data contained in the memory. However, it is clear that if the memory is an electrically recordable memory (RAM or EPROM or EEPROM), the contacts are also used to introduce data into the memory cells for writing. Since this in no way changes the problem of redundancy, we shall refer hereinafter to reading only, to prevent the description from becoming too cumbersome. Should it become necessary to take account of the writing operation as well, it will suffice to add on the elements necessary for writing and, especially, writing amplifiers connected between the contacts and the sets of columns.
In simpler embodiments, a single data reading amplifier corresponds to each contact.
FIG. 1 gives a very schematic view of a memory of this type. The memory is organised in z-bit words. There are z output contacts (P0 to P3), z reading amplifiers (A0 to A3), and z sets of columns each corresponding to a respective amplifier and contact. Each set has p columns of cells, and each column has n cells, i.e. the memory has n rows of cells.
There is a line (row) decoder DL designed to receive a line (row) address AL and select to one among n rows as a function of this address. There is a column decoder DC designed to receive a column address AC and to select one among p columns as a function of this address. The selection of a column address designates not just a single column but one column in each of the z sets, and connects this column to the reading amplifier and hence to the corresponding output contact. The application of a line address and a column address therefore sets up a z-bit word, coming from z columns, at the outputs. These z columns are distributed among the z sets: they all occupy the same column order number (among p possible column order numbers) in the different sets. The column address actually designates one determined column order number among p, for all the sets simultaneously.
The memory may include redundant rows (not shown for in this invention we are concerned purely with column redundancy) and redundant columns. For example, one group of redundant columns is provided for each of the z sets. The groups of redundant columns, given the general references CR0 to CR3, are controlled by a redundancy activation circuit CAR. This circuit receives the column addresses AC, checks whether they correspond to a defective column address and, if this is the case, deactivates the column decoder DC and selects a redundancy column as a replacement.
Since there is little space available in the memory, it is commonly seen, in practice, that the selection circuit designates one redundancy column simultaneously in each of the groups CR0 to CR3 (just as the column decoder DC simultaneously selects one column of each set). However, this means that, when a column is defective in a particular set, not only this column but all the columns having the same column address and forming part of the other sets are replaced. Provision could be made for another organisation of redundancy, wherein only the defective column is replaced, but this would imply the use of additional and fairly complicated routing or branching logic circuits for which there is generally no place in the integrated circuit (since such circuits take up a great deal of space in the immediate periphery of the array of memory cells.
The analogous organisation of the column redundancy may be more complicated in differently organised memories, especially memories which, by virtue of their high storage capacity and their integration density, have several reading amplifiers (2 or 4 or even more) per data contact. One address bit (or two or more) is reserved for the selection of the reading amplifier. The set of columns associated with each contact is now divided into several groups, each corresponding to a respective reading amplifier.
A memory such as this is shown in FIG. 2. The organisation of the rows and the line decoder are not shown, since only the layout of the columns concerns the column redundancy.
There are z sets of columns, designated by E0 to E3(z=3 in this example), each corresponding to a respective contact P0 to P3. Each set includes k groups (here k=2) and each group (within a set) is connected through its own respective amplifier to the contact that is associated with the set. The groups are designated by G0a and G0b for the first set E0, and by G1a and G1b for the second set E1, etc. The amplifiers are designated by A0a and A0b for the first set E0, and by A1a and A1b for the second set E etc.
Each group (G0a, G0b, G1a, etc) has p columns. The numbers of the p columns within a group will be referred to by their column order number (0 through p-1). The application of a word to the z outputs of the memory is done by the selection of a line address AL, a column address AC (specifying the column order number) and a post-selection address (corresponding to a "group order number"). The line address AL designates a row of cells. The column address AC designates one the p columns in each of the groups in each set i.e. k times z columns in all, the thus designated columns all having the same column order number among p column order numbers. Finally, the post-selection address AP defines one among k amplifiers in each set or, in what amounts to the same thing, one group order number of the k group order numbers. The consequence of this is the selection of one among k amplifiers in each set, i.e. a total of z amplifiers all having the same group order number among order numbers. The item sent to the data contacts will be a z-bit word coming from columns all having the same column order number (defined by AC) in the groups to which they belong, the groups themselves all having the same group order number (defined by AP) in the sets to which they belong.
FIG. 2 shows how the selection of columns and the post-selection are done from the address of a word that includes (in addition to the line address AL) the two address parts AC and AP.
Associated with each group of columns G0a, G0b to G3a, G3b, there is provision for a respective group of redundancy columns CR0a, CR0b to CR3a, CR3b.
Each group of redundancy columns includes r columns which means that, with one group, it is possible, in principle, to repair r defective columns. However, as shall be seen, the architecture does not make it possible to repair a total number of columns equal to z times k times r (z.cndot.k.cndot.r) although there are z times k times r redundancy columns. Indeed, for the same reasons as those indicated with reference to FIG. 1, the redundancy column selection circuit will select one among r columns simultaneously in all the groups, so that r defective columns will be repaired at the most. In the example shown, r=2: there are two redundancy columns in each of the two groups of each of the four sets.
FIG. 2 indicates the overall constitution of the redundancy column selection circuit: it has a comparator (COMP) receiving the column address AC and comparing this address with addresses stored in a register for storing addresses of defective columns (RS). If there is coincidence, the comparator deactivates the column decoder DC to prevent it from selecting the deactivated column and activates a redundant column selection circuit CSR. Depending on the result of the comparison, this circuit CSR selects one of the r redundancy columns of each set, simultaneously for all the sets. It is therefore all the redundancy columns of a given redundancy order number (among r possible redundancy order numbers) of the various groups CR0a, CR0b to CR3a, CR3b that are selected.
In this architecture, the address storage register RS has a maximum of r memories, each making it possible to store the address of one among p columns. The effectively stored address is the column address AC of a defective column, independently of the group to which it belongs. All the columns having a same column address AC are replaced by redundancy columns having the same order number among r order numbers. There are z.cndot.k replacements for each defective column.
There are several approaches to increasing the possibilities of replacement of defective columns, this increase being desirable when the size of the memory increases:
the first approach obviously consists in increasing r, but this greatly increases the size of the memory since there are r times k times z redundant columns. Furthermore, this entails a risk as the redundant columns themselves may be defective. PA1 the second approach consists in making the redundancy selection circuit capable of selecting any redundancy column without distinction and of routing it towards any amplifier whatsoever, without having to select one column simultaneously in every group. But this approach uses many routing or branching circuits, precisely at places close to the column outputs where there is not a great deal of space. PA1 a third possible approach is shown in FIG. 3. It consists in using a selection circuit CSR which separately controls the redundancy columns of the k different groups. For each defective column, the selection circuit will designate one among the k.cndot.r columns in each set, and not merely one among the r columns in each group. Only redundancy columns which have the same column and group order number will be selected. To illustrate this, the second redundant column, for example, can be selected among the groups of redundant columns CR0a, CR1a, CR2a, CR3a but without also selecting the second redundant column of the other groups CR0b to CR3b. In FIG. 2, all the second redundancy columns of all the groups CR0a, CR0b to CR3a, CR3b are necessarily selected. Hence, generally speaking, the advantage of the structure of FIG. 3 over that of FIG. 2 is that, the possibilities of redundancy are multiplied by k without any increase in the total number of redundant columns. However there are also disadvantages it is difficult to design such memories, because of the scarcity of space available in the immediate vicinity of the network of cells and decoders. The comparator and the selection circuit CSR are more complicated, and it is necessary to have at least k times r output lines for the circuit CSR instead of r lines only. PA1 a network of memory elements organised in n rows and z sets of k groups of p columns, where n, z, k and p are different from one, each set corresponding to a respective data contact among z contacts, and each group corresponding to a respective reading amplifier among k amplifiers connected to this contact, in such a way that a data item of a column of a given group in a given set is applied to the contact corresponding to this set by the amplifier corresponding to this group, PA1 a column decoder to select one among p columns simultaneously in all the groups of all the sets, and a post-selection means to select one among k amplifiers simultaneously in all the sets, as a function of the reception, by the memory, of one address AC among p column addresses, and of one group address AP among k, this group address defining one group order number in each set, PA1 wherein said redundant column activation circuit comprises: